مصطلحات الجيل السادس من المعالجات

أمير النهار السبت سبتمبر 23, 2017 9:54 am

السلام عليكم ورحمة الله وبركاته

ASPM: Active State Power Management

Cbo: Caching Agent (also referred to as CA). It is a term used for the internal logic

providing ring interface to LLC and Core. The Cbo is a functional unit in the

processor

DDR4: Fourth generation Double Data Rate SDRAM memory technology

DMA: Direct Memory Access

DMI3: Direct Media Interface Gen2 operating at PCI Express 3.0 speed

DSB: Data Stream Buffer. Part of the processor core architecture

DTLB: Data Translation Look-aside Buffer. Part of the processor core architecture

DTS: Digital Thermal Sensor

Enhanced IntelSpeedStep

Technology: Allows the operating system to reduce power consumption when performance is not needed

Execute Disable Bit: The Execute Disable bit allows memory to be marked as executable or nonexecutable,when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overallsecurity of the system. See the Intel

64 and IA-32 Architectures Software Developer's Manuals for more detailed information

Functional Operation: Refers to the normal operating conditions in which all processor specifications,including DC, AC, system bus, signal quality, mechanical, and thermal, are

satisfied

GSSE: Extension of the SSE/SSE2 (Streaming SIMD Extensions) floating point

instruction set to 256b operands

(HA: Home Agent (HA

ICU: Instruction Cache Unit. Part of the processor core architecture

IFU: Instruction Fetch Unit. Part of the processor core

IIO: The Integrated I/O Controller. An I/O controller that is integrated in the

processor die

IMC: The Integrated Memory Controller. A Memory Controller that is integrated in the

processor die

Integrated Heat Spreader(IHS): A component of the processor package used to enhance the thermal

performance of the package. Component thermal solutions interface with the

processor at the IHS surface

Intel

64 Technology: 64-bit memory extensions to the IA-32 architecture. Further details on Intel 64 architecture and programming model

Intel

Core

i7 processor family for LGA2011-v3 Socket processor: Intel's 22-nm process based product. The processor supports Efficient Performance High-End Desktop platforms

Intel

ME: Intel

Management Engine

Intel

Turbo Boost Technology: A feature that opportunistically enables the processor to run a faster frequency.This results in increased performance of both single and multi-threaded

applications

Intel

TXT: Intel

Trusted Execution Technology

Intel

Virtualization Technology (Intel

VT): Processor Virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform

Intel

VT-d: Intel

Virtualization Technology (Intel

VT) for Directed I/O. Intel VT-d is a

hardware assist, under system software (Virtual Machine Manager or operating system) control, for enabling I/O device Virtualization. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d

IOV: I/O Virtualization

IQ: Instruction Queue. Part of the core architecture

IVR: Integrated Voltage Regulation (IVR): The processor supports several integrated voltage regulators

Jitter: Any timing variation of a transition edge or edges from the defined Unit Interval

(UI)

LGA2011-v3 Socket: The 2011-v3 land FC-LGA package mates with the system board through this

surface mount, 2011-v3 contact socket

LLC: Last Level Cache

LRDIMM: Load Reduced Dual In-line Memory Module

LRU: Least Recently Used. A term used in conjunction with cache allocation policy

MESIF: Modified/Exclusive/Shared/Invalid/Forwarded. States used in conjunction with cache coherency

MLC: Mid Level Cache.

NCTF: Non-Critical to Function: NCTF locations are typically redundant ground or noncritical

reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality

PCH: Platform Controller Hub. The next generation chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security and storage features

PCI Express* 2.0: PCI Express Generation 2.0

PCI Express* 3.0: The third generation PCI Express specification that operates at twice the speed of PCI Express 2.0 (8 Gb/s); PCI Express 3.0 is completely backward compatible

with PCI Express 1.0 and 2.0

PECI: Platform Environment Control Interface

Processor: Includes the 64-bit cores, uncore, I/Os, and package

Processor Core: The term "processor core" refers to Si die itself which can contain multiple

execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the L3 cache

Rank: A unit of DRAM corresponding four to eight devices in parallel. These devices are

usually, but not always, mounted on a single side of a DDR4 DIMM

RDIMM: Registered Dual In-line Memory Module.

RTID: Request Transaction IDs are credits issued by the Cbo to track outstanding

transaction, and the RTIDs allocated to a Cbo are topology dependent

SCI: System Control Interrupt. Used in ACPI protocol

SKU: Stock Keeping Unit (SKU) is a subset of a processor type with specific features

electrical, power and thermal specifications. Not all features are supported on all

SKUs. A SKU is based on specific use condition assumption

SMBus: System Management Bus. A two-wire interface through which simple system and power management related devices can communicate with the rest of the system

(SSE: Intel

Streaming SIMD Extensions (Intel

SSE

STD: Suspend-to-Disk

Storage Conditions: A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to "free air" (that is, unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material

STR: Suspend-to-RAM

SVID: Serial Voltage Identification

TAC: Thermal Averaging Constant

TCC: Thermal Control Circuit

TDP: Thermal Design Power

TLP: Transaction Layer Packet

TSOD: Temperature Sensor On DIMM

UDIMM: Unbuffered Dual In-line Memory Module

Uncore: The portion of the processor comprising the shared LLC cache, IMC, HA, PCU, Ubox, and IIO link interface

Unit Interval: Signaling convention that is binary and unidirectional. In this binary signaling

one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If a number of edges are collected at instances t 1 , t 2 , t n ,...., t k then the UI at instance "n" is defined as: UI n = t n - t n-1

VCCD: DDR power rail

VCCIN: Primary voltage input to the voltage regulators integrated into the processor

VCCIO_IN: IO voltage supply input

VSS: Processor ground

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